Scan-chain-based design has been widely adopted as the primary DFT technique for testing large VLSI circuits. In general, scan-chain-based designs improve the testability of a circuit and hence can reduce the time for test generation and test application. Furthermore, because internal state elements are more easily observed and controlled in scan-chain-based designs, scan-chain-based diagnosis techniques can significantly improve the efficiency and effectiveness of identifying the root cause of one or more logic failures in a circuit. Thus, scan-chain-based logic diagnosis can be used to help accelerate product yield analysis and ramp up.
Scan-chain-based logic diagnosis typically assumes that the scan chains of a design are working properly. Recently, however, scan chain failures have become an important issue for yield analysis and product ramp up. For example, a defect in a scan chain can cause wrong values to be captured into or shifted out of a scan cell.
Conventional scan chain fault diagnosis techniques can be classified into three categories: tester-based, hardware-based, and software-based diagnosis techniques. In general, tester-based diagnosis techniques use a tester to control the test conditions and load values that are loaded into a faulty scan chain. By observing the defective responses from different test conditions, failing scan cells can be identified. Tester-based diagnosis techniques, however, are usually very time-consuming. Hardware-based diagnosis techniques typically involve modifying conventional scan chains to help isolate failing scan cells. Hardware-based diagnosis techniques can be effective in isolating scan chain defects, but these techniques require specially designed scan chains with extra hardware overhead which may not be acceptable. Software-based techniques use algorithmic diagnosis procedures to identify failing scan cells. In general, software-based diagnosis techniques do not require special scan chains and can be applied to general scan designs.
Successful scan chain fault diagnosis is dependent in part on the number of tester failures collected for a failing chip. In practice, production test patterns are often used to collect tester failures for scan chain and logic failure diagnosis. Regular production test patterns typically focus on a pass/fail evaluation of a circuit under test, however, and are not optimized for diagnosis purposes. For example, statistics on chain diagnosis for more than 100 die with failing chains have shown that with production scan test patterns, only about 23% of the scan chain diagnosis cases produce fewer than three scan cell candidates.
Accordingly, there is a need to improve scan chain diagnosis by generating and using higher quality test patterns for detecting scan chain failures.